HIRE-RISC
Funding acknowledgment
Advanced Research Project

HIRE-RISC

High Reliability Modules for RISC-V Architecture

Pioneering High-Reliability Solutions for RISC-V Architecture

Applying advanced hardening techniques to RISC-V architecture, generating commercial-ready intellectual property for the rapidly growing RISC-V processor market.

TRL2-3
Starting Point
TRL5
Target Goal
Research Objectives

Strategic Goals & Methodology

A comprehensive approach to developing high-reliability RISC-V solutions through innovative research and technological advancement.

ionicons-v5-d

From RENASER4 to HIRE-RISC

HIRE-RISC builds on the outcomes of RENASER4 (2020–2023), which addressed hardening of heterogeneous SoPC/MPSoC systems in radiation environments and developed early reliability analysis models and tools. This foundation is now transferred to the RISC-V architecture to progress from TRL 2–3 to TRL 5 through precompetitive IP, prototypes, and radiation-based validation.


IP Development

Development of precompetitive IP modules for RISC-V hardening, creating valuable intellectual property assets for the expanding processor market.

Prototyping

High-reliability single-core and multi-core RISC-V systems as proof-of-concept and technological demonstrators for industrial applications.

Validation

Comprehensive validation using radiation test experiments, ensuring reliability and performance under extreme environmental conditions.

Commercialization

Development of sustainable business models based on intellectual property protection and strategic licensing arrangements.

Research Teams

Collaborative Subprojects

Two specialized teams advancing hardware and software reliability solutions for RISC-V architectures.

PDC2023-145852-C21

Hardware Reliability

Módulos Hardware de Alta Fiabilidad para RISC-V

Hardware-level reliability modules and hardening techniques specifically designed for RISC-V processor architectures.

Researchers
Mario García Valderas
Luis Entrena Arrontes
PDC2023-145852-C22

Software Reliability

Módulos Software de Alta Fiabilidad para RISC-V

Software-level reliability solutions and hardening techniques for RISC-V systems and applications.

Researchers
Sergio A. Cuenca Asensi
Antonio Martínez Álvarez
Research Output

Publications & Intellectual Property

Comprehensive documentation of research findings and technological innovations from the HIRE-RISC project.

Academic Publications

Research findings and technological advances in RISC-V reliability and hardening techniques through peer-reviewed publications.

RADECS 2025
Conference Paper

"Hardware Hardening Techniques for RISC-V Processors Under Radiation"

M. García-Valderas, L. Entrena, et al. — Radiation Effects on Components and Systems Conference

Submitted • September 2025
Experimental Results
March 2025

Radiation Testing Campaign - Sevilla Facility

Comprehensive SEU/SET characterization of RISC-V reliability modules

Centro Nacional de Aceleradores (CNA), Sevilla
3
Journal Articles
2
Conference Papers

Intellectual Property

Strategic development and protection of intellectual property assets for commercial exploitation.

Public Repositories

COAST portado a LLVM — Open source contributions

IP Protection

Software registrations and hardware patents

HIREST Research Group

High Reliability and Safety Technologies research group

Social Media

Recent Updates & Research Progress

Follow our latest research developments, experimental results, and project milestones through our social media presence.

Recent LinkedIn Updates

New Radiation Testing Campaign at CNA

We have just completed a new radiation test campaign at the #CentroNacionaldeAceleradores (CNA) in Seville. This work is part of the ongoing project 'HIRE-RISC: high reliability software modules for...'

Second Radiation Campaign at CNA

🚀 We've just completed our second radiation campaign of the year at the Centro Nacional de Aceleradores (CNA)! In this campaign, we evaluated the reliability of different LSTM...